1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors having strained channel regions by using embedded semiconductor alloys, such as silicon/germanium, to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element for complex circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for maintaining a high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby enabling a performance improvement that is comparable with the advance to a technology standard requiring extremely scaled critical dimensions, while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium material next to the channel region to induce a compressive stress that may result in a corresponding strain. When forming the silicon/germanium material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Although this technique provides significant advantages in view of performance gain of P-channel transistors and thus of the entire CMOS device, it turns out, however, that a further increase of the strain component in the channel region may be difficult to achieve by reducing the lateral offset of the silicon/germanium alloy with respect to the channel region without compromising integrity of the gate electrode structure, as will now be described in more detail with reference to FIGS. 1a-1c to more clearly demonstrate one conventional approach for forming a silicon/germanium alloy.
FIG. 1a schematically illustrates a cross-sectional view of a conventional semiconductor device 100 at an early manufacturing stage. As illustrated, the semiconductor device 100 comprises a substrate 101, such as a silicon substrate, above which may be formed a buried insulating layer (not shown), if a silicon-on-insulator (SOI) configuration is considered. Furthermore, a silicon-based semiconductor layer 102 is formed above the substrate 101 and represents an “active” semiconductor material for forming therein and thereon circuit elements, such as transistors and the like. As illustrated, the semiconductor layer 102 comprises a first active region 102A and a second active region 102B which are separated by an isolation structure 103, such as a shallow trench isolation and the like. The active region 102A represents an appropriately doped semiconductor material for forming therein and thereabove a P-channel transistor 150A, while the active region 102B may have an appropriate dopant concentration so as to provide the basic characteristics for an N-channel transistor 150B. In the manufacturing stage shown, the transistors 150A, 150B comprise a gate electrode structure 151, which may include a gate electrode material 151A, a cap layer 151B formed on a top surface of the gate electrode material 151A and a gate insulation layer 151C, which separates the gate electrode material 151A from a channel region 152 of the corresponding active regions 102A, 102B. Furthermore, a spacer element 104A is formed on sidewalls of the gate electrode structure 151 of the P-channel transistor 150A, possibly in combination with an etch stop liner 105. On the other hand, the N-channel transistor 150B is covered by a spacer layer 104, possibly in combination with the etch stop liner 105.
The semiconductor device 100 may be formed according to the following process techniques in compliance with well-established conventional approaches for providing a silicon/germanium alloy. After defining the active regions 102A, 102B by forming the isolation structure 103 and performing appropriate implantation sequences in order to establish the basic dopant concentration, the gate electrode structures 151 may be formed by providing an appropriate material for the gate insulation layers 151C followed by the deposition of a gate electrode material 151A. Furthermore, material of the cap layers 151B may be deposited. For this purpose, well-established oxidation, surface treatments and deposition techniques may be used, depending on the required materials and characteristics thereof. For example, the material for the gate insulation layer 151C may be formed by oxidation and/or deposition or surface treatment, for instance for forming silicon dioxide-based materials having a thickness of approximately one to several nanometers in sophisticated semiconductor devices. In other cases, high-k dielectric materials may be used, such as hafnium oxide and the like, which may typically have a dielectric constant of 10 or higher, thereby increasing the capacitive coupling of the gate electrode material 151A to the channel region 152 for a given physical thickness of the gate dielectric material. Thereafter, any appropriate material for the gate electrode 151A may be provided, for instance in the form of polysilicon and the like, followed by the deposition of the cap material 151B, which may be provided in the form of a silicon nitride material and the like. During the subsequent patterning of these material layers, sophisticated lithography techniques and etch processes may be used in order to obtain the gate electrode structure 151 with a desired gate length according to the design rules for the device 100. Next, the etch stop liner 105 may be formed by deposition and/or oxidation, followed by the deposition of the spacer layer 104, typically provided in the form of a silicon nitride material, which may be deposited by thermally activated chemical vapor deposition (CVD) recipes, plasma assisted processes and the like. When depositing the spacer layer 104, a thickness thereof may be selected in view of a desired width 104W of the spacer element 104A, which in turn may determine an offset of the silicon/germanium alloy to be formed in the active region 102A in a later manufacturing stage. In sophisticated applications, the width 104W is desirably reduced in order to enhance the strain-inducing mechanism obtained by the silicon/germanium material. However, although a reduced thickness of the spacer layer 104 may be desirable in view of a performance gain of the transistor 150A, a certain minimum value for the thickness of the spacer layer 104 may have to be provided in view of maintaining overall integrity of the gate electrode material 151A and of the gate insulation layer 151C during the further processing in providing the strained silicon/germanium alloy. Consequently, typically a thickness of 10-30 nm may be selected, thereby providing a required process margin in view of the subsequent manufacturing processes. After forming the spacer layer 104, an etch mask 106 is provided on the basis of photolithography techniques in order to cover the transistor 150B and the corresponding portion of the spacer layer 104, while exposing the transistor 150A to an etch ambient 107 that is designed to selectively remove material of the spacer layer 104, thereby forming the spacer element 104A. The etch process 107 may be performed on the basis of well-established plasma assisted anisotropic etch techniques, wherein, if required, a control of the etch process may be accomplished on the basis of the etch stop liner 105. Thereafter, the liner 105 may be removed and a further etch process or a further step of the process 107 may be performed on the basis of appropriately selected etch parameters and an anisotropic etch chemistry for etching into the active region 102A selectively to the spacer 104A and the isolation structure 103. For example, highly selective anisotropic etch techniques for removing silicon selectively to oxide and nitride are well established in the art.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, corresponding cavities 108 are formed adjacent to the gate electrode structure 151 and the spacer element 104A, wherein, due to the anisotropic nature of the preceding plasma assisted etch process, substantially vertical sidewalls 108S are obtained so that a lateral offset of the cavities 108 and thus of any silicon/germanium alloy still to be formed in a later manufacturing stage with respect to the gate electrode material 151A is substantially determined by the width 104W of the spacer 104A, possibly in combination with the thickness of the etch stop liner 105, if provided. After the corresponding cavity etch process or prior to the process, the etch mask 106 may be removed.
As previously discussed, the efficiency of the strain-inducing mechanism obtained by the strain-inducing semiconductor alloy, such as the silicon/germanium alloy to be filled into the cavities 108, significantly depends on the internal strain level of the semiconductor alloy and on the amount and the lateral distance of the semiconductor alloy with respect to the channel region 152. Since the depth of the cavities 108 is substantially determined by the initial thickness of the semiconductor layer 102, in particular when an SOI configuration is considered, further enhancement of the strain-inducing mechanism may typically be accomplished by reducing the lateral offset for a given type of strain-inducing semiconductor alloy. Consequently, the width 104W of the spacer 104A is typically reduced, wherein, however, further process related constraints may have to be respected, which may set the limit for a minimum width 104W. For example, the spacer 104A may provide integrity of the gate insulation layer 151C and the gate electrode material 151A during the preceding anisotropic etch process and also during a subsequent process sequence for preparing the semiconductor device 100 for the selective epitaxial deposition of the silicon/germanium material. For example, in sophisticated applications, frequently, advanced gate electrode structures comprising a high-k dielectric material in the gate insulation layer 151C may be used in combination with a metal-containing electrode material, which may have to be reliably confined in order to maintain the characteristics thereof, for instance with respect to relative permittivity, work function and the like. In other cases, an extremely thin silicon dioxide-based material may be used, the exposure of which to any etch ambient may result in significant damage and thus unpredictable device characteristics of the transistor 150A. Furthermore, in a subsequent manufacturing stage, the device 100 may be heated to an elevated temperature of, for instance, 800° C. and higher in order to prepare the device 100 for being loaded into a chamber or process ambient that is appropriate for performing a selective epitaxial growth process. For example, a native oxide which may have formed on exposed surface areas in the cavities 108 may be removed, wherein, however, a certain degree of silicon reflow may occur and may thus result in a certain deformation of the shape of the cavities 108. Consequently, a further reduction of the width 104W may be associated with a high probability of inducing damage in the gate electrode structure 151, which may not be compatible with sophisticated manufacturing flows.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, i.e., during a selective epitaxial growth process 110, during which a silicon/germanium alloy 111 is formed in the cavities 108 with a lateral offset with respect to the gate electrode material 151A that is substantially defined by the width 104W, as previously explained. Consequently, based on a predefined fraction of germanium species incorporated in the material 111, the internal strain level is substantially determined by the lateral offset of the material 111 with respect to material in the channel region 152. However, upon further scaling the overall transistor dimensions, a further increase of the strain transfer efficiency may not be scalable on the basis of the conventional process strategy as described above.
In view of the situation described above, the present disclosure relates to semiconductor devices and processes in which an embedded semiconductor alloy may be positioned in close proximity to the channel region, while avoiding or at least reducing one or more of the problems identified above.